About linking

[yasar11732]

Hi,

I am new to c++ and also learning makefiles now. I have a concern about something, here is my makefile:

IDIR :=include
CC :=g++ -Wall
CFLAGS:=-I$(IDIR)
LIBS:=-lSDL -lSDL_image

OBJDIR :=.obj
SRCDIR :=src

$(OBJDIR)/%.o : $(SRCDIR)/%.cpp
	$(CC) -c -o $@ $< $(CFLAGS)

all: set_up helloworld helloworld2
set_up : .obj/set_up.o $(DEPS)
	$(CC) -o $@ $^ $(CFLAGS) $(LIBS)
helloworld : .obj/helloworld.o
	$(CC) -o $@ $^ $(CFLAGS) $(LIBS)
helloworld2 : .obj/helloworld2.o
	$(CC) -o $@ $^ $(CFLAGS) $(LIBS)

.PHONY: clean

clean:
	rm -fv absolutevalue $(OBJDIR)/*.o *~ core $(IDIR)/*~ *swp */

As you can see, even though not all of my executables need SDL_image library, I am linking all my executables against it. Does it add unnecessary things to other files that don't need that spesific library? Should I spesicify linking separately for each rule?

[hanst99]

What make dialect is this? That's not quite the syntax I'm used to.

Anyways: If you have different executables, why are you using the same makefiles for them? If you insist on putting them all in the same makefile, then just use different options for each as appropitiate.

[Peter87]

No the executable file will not be affected. After testing it appears I was wrong at least in the case of dynamic linking.

[hanst99]

Actually, a non optimizing will just bake the entire library into the executable if you're linking statically, and if you're linking dynamically you will create dependiencies upon libraries that aren't even used. That's not what I'd call "not affected".

[yasar11732]

What make dialect is this? That's not quite the syntax I'm used to.

Anyways: If you have different executables, why are you using the same makefiles for them? If you insist on putting them all in the same makefile, then just use different options for each as appropitiate.

I am running this using gnu make. I have red http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/ and some of "info make". I am not absolutely sure that I am using right syntax, but it works.

As for single makefile, I am following online tutorials, each executable is short, and somewhat related to others. I thought using a single makefile would be easiest. I am not very experienced about concept of makefiles, I guess I should have used different makefiles for each executable.

By looking at the suggestion, does that mean using unnecessary links hurts programs in any way?

Edit: I didn't see your second post when I post this. I guess I understand now.

[yasar11732]

One last thing, How do I know if I am linking statically or dynamically? I am using gcc 4.6.2 and compiling like this:

g++ -Wall -c -o .obj/helloworld2.o src/helloworld2.cpp
g++ -Wall -o helloworld2 .obj/helloworld2.o -lSDL

[Peter87]

gcc uses dynamic linking by default

[yasar11732]

If I wanted to specify static linking, what would be option for it? I am trying google, but couldn't find right search term for it.

[Peter87]

You can use the flag -static to force static linking

[hanst99]

I swear GNU Make used = instead of := for variable assignment last time I used it. Either I'm getting senile, there are 2 GNU Makes, or GNU Make for some reason has 2 assignment operators.

[yasar11732]

This https://www.gnu.org/software/make/manual/html_node/Prerequisite-Types.html#Prerequisite-Types uses := as variable assignment operator. I copied that from there.

[Peter87]

There is some difference between the two.
http://www.gnu.org/software/make/manual/html_node/Reading-Makefiles.html