Improve Makefile

Hi,

I have a proyect folder like this:
/proyect = {/src /help /bin /obj main.cpp}

My makefile build the exec file into bin. I still have something wrong and it always builds everything from the start. Every *.o is build again even if I dont touch the files. The makefile should check what have been modyfied and only build those objects :O.

This is my makefile. Any solution and general inprovements? Thanks :)


# Configuracion de C++
CC      = g++
CFLAGS  = -c -Wall
FLAGS   = 

# Variables
TARGET   = criptografia
DIR_SRC  = src/
DIR_HELP = help/
DIR_OBJ  = obj/
DIR_BIN  = bin/

OBJ = main.o help.o P1.o P2.o

$(TARGET): $(OBJ)
	$(CC) $(FLAGS) $(addprefix $(DIR_OBJ), $(OBJ)) -o $(DIR_BIN)$@

main.o: main.cpp
	$(CC) $(CFLAGS) $< -o $(DIR_OBJ)$@

%.o: $(DIR_HELP)%.cpp $(DIR_HELP)%.h
	$(CC) $(CFLAGS) $< -o $(DIR_OBJ)$@

%.o: $(DIR_SRC)%.cpp $(DIR_SRC)%.h 
	$(CC) $(CFLAGS) $< -o $(DIR_OBJ)$@

clean:
	rm -Rf $(DIR_OBJ)*.o $(DIR_BIN)$(TARGET)
Haha, I autoresolved the first problem. Problem was that the target has to be the *.o file with his location. My makefile now looks like this:


# Configuracion de C++
CC      = g++
CFLAGS  = -c -Wall
FLAGS   = 

# Variables
TARGET   = criptografia
DIR_SRC  = src/
DIR_HELP = help/
DIR_OBJ  = obj/
DIR_BIN  = bin/

OBJ = main.o help.o P1.o P2.o

$(DIR_BIN)$(TARGET): $(addprefix $(DIR_OBJ), $(OBJ))
	$(CC) $(FLAGS) $? -o $@

$(DIR_OBJ)main.o: main.cpp
	$(CC) $(CFLAGS) $< -o $@

$(DIR_OBJ)%.o: $(DIR_HELP)%.cpp $(DIR_HELP)%.h
	$(CC) $(CFLAGS) $< -o $@

$(DIR_OBJ)%.o: $(DIR_SRC)%.cpp $(DIR_SRC)%.h 
	$(CC) $(CFLAGS) $< -o $@

clean:
	rm -Rf $(DIR_OBJ)*.o $(DIR_BIN)$(TARGET)


But now, the problem is that when I modify any source file, it gets compiled right, but it linkes wrong after. It happens something like this:


g++ -c -Wall src/P1.cpp -o obj/P1.o
g++  obj/P1.o -o bin/criptografia
/usr/lib/gcc/i686-linux-gnu/4.4.5/../../../../lib/crt1.o: In function `_start':
(.text+0x18): undefined reference to `main'
...


The error is because it needs to link the other objects aswell. But I dont know how to fix it. Any ideas or improvements? Thanks again :)
1
2
$(DIR_OBJ)main.o: main.cpp
	$(CC) $(CFLAGS) $(OBJ) $< -o $@


I am not very fluent with makefile-ish, but that should work... I think.
Typically, CXX is used for C++ and CC is used for C. Simiarly, I think CXXFLAGS, etc. are commonplace.
The C stood for C? I always thought it stood for "Compiler"... or rather, like:

CC = C - Compiler
RC = Resource Compiler
etc


Good that no one ever had to read my makefiles.
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