Google search is your friend. Just enter "Makefile tutorial" and you should see a few examples to learn.
Please note the latter Make version support even more functionalities than what we usually know. I don't know if it support conditional and branching logic inside a Makefile ?
I need to understand the meaning of each line. I have looked for tutorials but I could understand. Could you please write to me the meaning of each line in a simple working makefile.
These are variables so that you can easily change the compiler or compiler flags in one place for all the rules, so the line, $(CC) $(CFLAGS) run.cpp gets translated into g++ -c -Wall run.cpp.
run-64bit: run.o monitor.o formatter.o logger.o
Says run-64bit depends on the following: run.o, monitor.o, formatter.o, and logger.o.
the next set of rules tells it how to build those dependencies:
run.o: run.cpp
$(CC) $(CFLAGS) run.cpp
...
Your file says that run-64bit depends on one object file and three header files:
run-64bit: run.o monitor.h formatter.h logger.h
You should be able to put the two side by side to see any other differences.