Hi all,
I'm relatively new to Makefiles, and while I can usually get them to work, I am a little confused about how make determines what files need to be recompiled.
Consider the following Makefile:
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|
CC=g++
all: hi.o
$(CC) -o hi hi.o
hi.o: hi.c hi.h
$(CC) -c hi.c
clean:
rm -f hi.o hi
|
This works exactly as I expect it to: if I invoke "make" it compiles hi.c into hi.o, links hi.o and produces the hi executable, and if I call "make" again, hi.c is NOT recompiled because make can tell it hasn't been altered since hi.o was created.
However, suppose I want to keep my top level folder less cluttered, so I create a folder to store the (not yet linked) object files? Then I have to alter the above Makefile somewhat:
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CC=g++
all: hi.o
$(CC) -o hi obj/hi.o
hi.o: hi.c hi.h
$(CC) -c hi.c -o obj/hi.o
clean:
rm -f obj/hi.o hi
|
This works just fine. However, if I invoke "make" a second time, without changing the source code hi.c or hi.h, hi.c is still recompiled. Does anyone see what about the second Makefile is causing this redundancy to occur?
Thanks in advance for any help/suggestions.
-Ben