Makefiles and folder structure

I'm having some trouble with my makefile rules. I'm sure that I can make it much simpler than it is but I'm not sure how.

My folder structure looks like this:
root
  \- bin - Contains binary outputs (executables, dynamic, and static libraries)
  |   \- liboutput.a
  \- inc - Contains an export of headers to be used with this library.
  |   \- <module>
  |        \- *.hpp
  \- int - Contains intermediate binaries (.o, .d)
  |   \- *.o
  |   \- *.d
  \- src - Contains all sources and headers in this library
      \- <module> - sources are split logically by smaller modules
          \- *.hpp
          \- *.cpp


These are the rules I'd like to follow:
1. for each <module> specified in the makefile: 
  A. Compile all src/<module>/*.cpp into int/*.o
  B. Copy all src/<module>/*.hpp into inc/<module>/*.hpp
2. Link all int/*.o to produce bin/output.a


My Makefile looks something like this:
CPPFILES = $(wildcard src/<module>/*.cpp)
OBJFILES = $(addprefix int/,$(notdir $(CPPFILES:.cpp=.o)))
    
all : $(OBJFILES)
    ar rvs bin/liboutput.a $(OBJFILES) \
        && cp src/<module>/*.hpp inc/<module>

int/%.o : src/<module>/%.cpp
    g++ -c -o $@ $<


However, you'll notice that <module> needs to be replaced with something more loopy. Does anyone have an idea of how I can accomplish that?
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