### Timing Diagrams

Hi guys,

so I decided to take a foray into microprocessor architecture, I understand for the most part the logic gates that make up various parts of a processor and have some idea on the inner workings albeit a very rudimentary understanding but one thing that has me stumped is the timing diagrams, I can't for the life of me understand what they're trying to convey.

I'm studying the well known zilog z80, and I literally have no idea how to read.interpret this timing diagram, I have looked online but I'm yet to find any good explanation of timing diagrams.

Just wondering if anybody has any experience with electronics might be able to steer me in the right direction.

The diagrams are on page 2 and 3 - https://www-users.cs.york.ac.uk/~pcc/Circuits/64180/docs/z180ch2.pdf
It's a plot of several signal values over time. Time progresses from left to right.

Phi is the first signal at the top of the diagram. It's also a square wave, and the pulses (the "peaks" of the square wave) are labelled. This suggests that phi is an input, some "clock signal" that the microprocessor pays attention to. Every time its logic level changes, the uP (microprocessor) kicks into action.

The timing diagram shows how the pins of the uP react to changes in phi. It doesn't say how fast these changes take in absolute terms, but it does show how they change relative to phi's transitions.

For example, if we look to the fifth trace from the top, the signal trace labelled /M1, we can tell that /M1 will become active (active low, logic 0) in response to T1's first rising edge, and that it will remain low until T3's rising edge, at which point it will be become inactive (inactive high, logic 1) in response.

A0-A19 is a collection of 20 pins, almost certainly the address bus, which will be driven mostly in response to software. It does indicate that the bus will transition in response to all of T1's rising edges.

Does this help? I don't know how much you already know about digital logic.

P.S., I'm talking about the very first diagram.
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Hi Mbozzi, I should have prefaced by saying my understanding of electronics is quite limited.

 The timing diagram shows how the pins of the uP react to changes in phi. It doesn't say how fast these changes take in absolute terms, but it does show how they change relative to phi's transitions. For example, if we look to the fifth trace from the top, the signal trace labelled /M1, we can tell that /M1 will become active (active low, logic 0) in response to T1's first rising edge, and that it will remain low until T3's rising edge, at which point it will be become inactive (inactive high, logic 1) in response.

That makes sense :)

 A0-A19 is a collection of 20 pins, almost certainly the address bus, which will be driven mostly in response to software. It does indicate that the bus will transition in response to all of T1's rising edges.

What I don't understand is, what is happening on the address lines within he first 3 clock cycles(T states),

The clock starts off at 0(low) and transitions to 1(high) but when looking at the address line the weird hexagon shape transitions into a new hexagon shape when t1 is high (not on the edge but when t1 is level)

@againtry, I tried that video but was unfamiliar with a lot of the terminology he used, I'm a complete novice to electronics.

Thanks
 What I don't understand is, what is happening on the address lines within he first 3 clock cycles(T states), The clock starts off at 0(low) and transitions to 1(high) but when looking at the address line the weird hexagon shape transitions into a new hexagon shape when t1 is high (not on the edge but when t1 is level)
You're looking at a slice of a cyclical process. The clock doesn't start low. Or rather, that's not what the diagram is saying. What you're seeing is the tail-end of the previous fetch loop, i.e. the low of the previous T2. What the diagram says about the address bus is
1. The fetch process takes 3 cycles: T1, T2, and T3.
2. During the high of T1 the various traces of the address bus are changing to the corresponding states of the address' bits. I.e. during the high of T1 the bus is in an undefined state, and can only be considered stable either on the falling edge of T1 or on its low.
3. Once stable, the address bus maintains its state for two and a half cycles, after which a new fetch starts and the bus becomes unstable again.
Oh okay that does actually make a little bit of sense but at the same time I'm not going to lie and say I completely understand the whole diagram,

I now understand that the trailing hexagon on the address line is from the previous cycle, and on the first cycle(T1) something is happening when the clock is level (1), but what does the hexagon mean on the address bus starting at the high end of t1? and between the falling edge of t2 and rising edge of t3 two dotted lines contain pc, what does this indicate? (Obviously I'm guessing PC stands for program counter but I'm not sure how this ties in)

and just below on the data lines, just before the second dotted line a box labeled opcode appears?

From my understanding the fetch cycle of a zillog z80 takes 3-5 cycles, and in those 3 cycles the processor will read the opcode (1 byte) from memory normally starting at address (0x0000) but I don't see how this timing diagram illustrates that.
Are you actually reading the text? The page just before the diagrams explain in words what the diagrams describe graphically.
 Figure 2-1 shows the instruction (op-code) fetch timing with no wait states. An op-code fetch cycle is externally indicated when the /M1 output pin is Low.
As I understand it, the dotted lines are highlighting that the memory request is fulfilled during the low of T2 and the data is available at the high of T3.
I understand that it's fetching an opcode yes but I'm having a hard time understanding the outputs in the diagram and how it pertains to it graphically.

 n the first half of T1, the address bus (A19-A0) is driven from the contents of the Program Counter (PC). Note that this is the translated address output of the on-chip MMU.

Driven is used a lot with electronics, what does the author mean by the address bus is driven by the contents of the program counter?

The PC is made up of memory cells. Each of those memory cells has an output pin that, when the cell is read, contains the state of the cell. "The address bus is driven from the contents of the program counter" means the traces the address bus consists of are connected to the output pins of the program counter.
"Drive" might be a somewhat colloquial term, but it hints that the "driven" circuit fragment acts as a low-impedance output.

If the term "impedance" means nothing to you, think of it nontechnically: a digital output is "driven" when it is "forcefully" set to some value (logic 0 or 1). It means that you can do some small amount of useful stuff with the output without need for some special buffer stage.

An example of a ("driven low") low-impedance logic 0 is a dead short to signal ground.
An example of a ("driven high") low-impedance logic 1 is a dead short to supply.
An example of a ("tri-stated") high-impedance circuit fragment is an open circuit.

The great thing about digital logic is that you don't need to care about the theory at all. It's really just plug-and-play, very easy to get started with.
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"The Z80 Microprocessor Architecture, Interfacing, Programming and Design"
Author(s): Ramesh Gaonkar

Thanks guys, I'm probably overthinking it and as Mbozzi said it's best to learn through hands on projects, I have an arduino on my shelf that's just gathering dust.

@Mbozzi would the following be an example of driving low, let's say we hook up 8 resisters to the data lines of a micro processor or MCU to set the value to all zeros?

 @mbozzi would the following be an example of driving low, let's say we hook up 8 resisters to the data lines of a micro processor or MCU to set the value to all zeros?

I wouldn't consider it so. The circuit I imagine consists of a resistor between signal ground and a digital input:

ground-resistor-input

An output can drive, while an input can be driven. In your example the data lines are the inputs, or at least that's what I assume you mean. Similarly, signal ground is the output -- a circuit fragment that always outputs logic 0.

In this configuration the resistor is called a "pull-down resistor", so the input pin is "pulled down", not "driven low".
From the name we can tell a resistor "resists", or "impedes" the flow of current, hence it has "high impedance". This is the deciding factor, because the term "driven" suggests a low impedance.

(Note that in digital electronics, typically, ideally, no current flows through digital inputs. Therefore the resistors aren't necessary this time. You could connect the input pins directly to signal ground with no ill effects. Without the resistors, the pins would be driven.)
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