Altera is Hiring Software Design Engineers in San Jose
Description
As a Senior Design Engineer, you will be involved in developing customer facing protocol based PHY IPs for high speed transceiver modules. You will also be involved in developing advanced VMM based verification modules for verifying the PHY IPs, and performing hardware tests and protocol compliance tests. In addition, you will be involved in developing transceiver reconfiguration solutions for the upcoming generation of device families as well. You will develop high speed transceiver Intellectual Property (IP) cores, such as PCI Express and 10 Gigabit Ethernet PCS IP. As Altera FPGAs expand into high speed and high bandwidth solutions, one of our big challenges is designing and implementing a protocol IP stack with an easy-to-use interface. As an IP engineer, you will be part of a dynamic and energetic team that pushes the design and technological boundaries in building high speed serial protocol IPs. As well as developing our current generation of IPs, you will also work with Altera’s hardware design teams in defining and developing the next generation of transceivers for Altera.
The successful candidate's minimum qualifications will include the following:
· BS in Computer Engineering, Electrical Engineering, or equivalent with a minimum of 2 years of experience
· Knowledge of VHDL or Verilog design and verification is required
· Good understanding of software programming principles including proficiency in C/C++
· Some understanding of transceivers and FPGA architecture
To apply, please follow this link:
http://tbe.taleo.net/NA3/ats/careers/requisition.jsp?org=ALTERA&cws=1&rid=294
As a Senior Design Engineer, you will be involved in developing customer facing protocol based PHY IPs for high speed transceiver modules. You will also be involved in developing advanced VMM based verification modules for verifying the PHY IPs, and performing hardware tests and protocol compliance tests. In addition, you will be involved in developing transceiver reconfiguration solutions for the upcoming generation of device families as well. You will develop high speed transceiver Intellectual Property (IP) cores, such as PCI Express and 10 Gigabit Ethernet PCS IP. As Altera FPGAs expand into high speed and high bandwidth solutions, one of our big challenges is designing and implementing a protocol IP stack with an easy-to-use interface. As an IP engineer, you will be part of a dynamic and energetic team that pushes the design and technological boundaries in building high speed serial protocol IPs. As well as developing our current generation of IPs, you will also work with Altera’s hardware design teams in defining and developing the next generation of transceivers for Altera.
The successful candidate's minimum qualifications will include the following:
· BS in Computer Engineering, Electrical Engineering, or equivalent with a minimum of 2 years of experience
· Knowledge of VHDL or Verilog design and verification is required
· Good understanding of software programming principles including proficiency in C/C++
· Some understanding of transceivers and FPGA architecture
To apply, please follow this link:
http://tbe.taleo.net/NA3/ats/careers/requisition.jsp?org=ALTERA&cws=1&rid=294
Topic archived. No new replies allowed.