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CHECK SUM Digits
Need some help with this calculation. I am supplied the keys and need to calculate the output
I think you xor key 1 to key 2 then again with all "0's" but I cant seem to get it
Left Key: 4F94 9175 07B5 52DF 0731 3E62 8901 49EA
Right Key: 7AAE 9191 9864 29BC 19C2 BC34 7FE5 2383
Check Digits: C00020
I think you xor key 1 to key 2 then again with all "0's" but I cant seem to get it
Left Key: 4F94 9175 07B5 52DF 0731 3E62 8901 49EA
Right Key: 7AAE 9191 9864 29BC 19C2 BC34 7FE5 2383
Check Digits: C00020
This is what was given to me but not sure.....
In this description of the algorithm, the two hexadecimal digits of the checksum are represented by P1 and P2 for the set of 32 hexadecimal digits D(1,2,.....,32). The letter i represents the increment.
To calculate the checksum, use this algorithm:
Set i = 0, and set P1 and P2 = 0 (hexadecimal).
Let P1 = Sum of P1 and D(i + 1). Let P2 = Sum of P2 and D(i + 2).
Let P1 = H(P1). Let P2 = H(P2).
Let i = i + 2. If i < 32, go to step 2; otherwise, go to step 5.
P1 equals the first checksum digit. P2 equals the second checksum digit.
To calculate this verification pattern, use this algorithm:
If the key part is an operational key part, exclusive OR the key part with the control vector for the key part's key type. See Appendix B. Control Vector Table, for a listing of control vectors by key type. If the key part is a master key part, do not exclusive OR it with a control vector.
Use the DES algorithm to encrypt the left half of the key part (either master key part or modified operational key part) under the key 4545 4545 4545 4545.
Exclusive OR the result of step 2 with the left half of the key part.
Use the result of step 3 as the DES key in the DES algorithm to encrypt the right half of the key part.
Exclusive OR the result of step 4 with the right half of the key part.
The resulting 64-bit value is the verification pattern.
The verification pattern for the master key appears on the Coprocessor Selection and Hardware Status panels. If a master key register is full, the panels display the master key verification pattern. The verification patterns for two identical master keys are the same. You can use the verification patterns to verify that master keys in two different key storage units are the same
In this description of the algorithm, the two hexadecimal digits of the checksum are represented by P1 and P2 for the set of 32 hexadecimal digits D(1,2,.....,32). The letter i represents the increment.
To calculate the checksum, use this algorithm:
Set i = 0, and set P1 and P2 = 0 (hexadecimal).
Let P1 = Sum of P1 and D(i + 1). Let P2 = Sum of P2 and D(i + 2).
Let P1 = H(P1). Let P2 = H(P2).
Let i = i + 2. If i < 32, go to step 2; otherwise, go to step 5.
P1 equals the first checksum digit. P2 equals the second checksum digit.
To calculate this verification pattern, use this algorithm:
If the key part is an operational key part, exclusive OR the key part with the control vector for the key part's key type. See Appendix B. Control Vector Table, for a listing of control vectors by key type. If the key part is a master key part, do not exclusive OR it with a control vector.
Use the DES algorithm to encrypt the left half of the key part (either master key part or modified operational key part) under the key 4545 4545 4545 4545.
Exclusive OR the result of step 2 with the left half of the key part.
Use the result of step 3 as the DES key in the DES algorithm to encrypt the right half of the key part.
Exclusive OR the result of step 4 with the right half of the key part.
The resulting 64-bit value is the verification pattern.
The verification pattern for the master key appears on the Coprocessor Selection and Hardware Status panels. If a master key register is full, the panels display the master key verification pattern. The verification patterns for two identical master keys are the same. You can use the verification patterns to verify that master keys in two different key storage units are the same
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