SystemC signals

[saggiatorius]

Hi, please let's look at the code below.
After that, please consider the problem of modelling the signal-level communication between master and slave:
1) How many signals are needed to implement the same semantics offered by the channel?
2) Please write the adapters' declaration between master and slave and the transmission signals, highlighting the interfaces to implement and the ports.

Thanks a lot,

Saggiatorius


__SystemC code_________________________

include "systemc.h"
#include <iostream>

class write_if: public sc_interface
{
  public:
    virtual void write(int dato)=0;
};

class canale: public sc_channel, public write_if
{
  public:
    sc_port<write_if> write_port;
    void write(int dato)
    {
      write_port->write(dato);
    }  
    SC_CTOR(canale){}
};

class slave: public sc_channel, public write_if
{
  public:
    void write(int dato)
    {
      cout << dato << endl;
    }
    SC_CTOR(slave){}
};

class master: public sc_module
{
  public:
    sc_port<write_if> write_port;
    sc_in<bool> clk;
    void action()
    {
      int a=0;
      wait();
      while(true)
      {
        write_port->write(a++);
        wait();
      }
    }
    SC_CTOR(master)
    {
      SC_CTHREAD(action,clk.pos());
    }
};

[jsmith]

Please repost the code using tags so it gets formatted. Also, please use indentation.

[saggiatorius]

include "systemc.h"
#include <iostream>

class write_if: public sc_interface
{
  public:
    virtual void write(int dato)=0;
};

class canale: public sc_channel, public write_if
{
  public:
    sc_port<write_if> write_port;
    void write(int dato)
    {
      write_port->write(dato);
    }  
    SC_CTOR(canale){}
};

class slave: public sc_channel, public write_if
{
  public:
    void write(int dato)
    {
      cout << dato << endl;
    }
    SC_CTOR(slave){}
};

class master: public sc_module
{
  public:
    sc_port<write_if> write_port;
    sc_in<bool> clk;
    void action()
    {
      int a=0;
      wait();
      while(true)
      {
        write_port->write(a++);
        wait();
      }
    }
    SC_CTOR(master)
    {
      SC_CTHREAD(action,clk.pos());
    }
};