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Project LOGIC SIMULATOR
Hi everyone! I'm studying c++ for university. I've to implement a Logic Simulator, which gets two input files: 1)input.txt regarding circuit's toplevel inputs; 2)description.txt concerning the structural description top level and internal of the circuit.
an exemple:
description.txt
NAME Full_adder
INPUTS 3
OUTPUTS 2
NETS 4
GATES
XOR2 U0 I0, I1, N0
XOR2 U1 N0, I2, O0
AND2 U2 N0, I2, N1
AND2 U3 I0, I1, N2
OR2 U4 N1, N2, O1
input.txt
011
000
110
111
Here what in brief I've done:
-Create a class FileManager that manages the two input files and creates 3 data structures: one concerning inputs, one the top level description, and the other one concerning the internal structural view of circuit
-Create a class Synthesizer that gets the 3 data-structures and synthesize the circuit as a sort of graph, in which the wiring with next gates are done by means of pointer to next gates.
In particulare for each line after "GATES" the synthesizer instatiates a logic gate described by a LogicGate class, and evaluetes which type of port is it: HEADER(inputs labeled as "Ix"), INTERNAL ("Nx") or TAIL. Then collects these logic gates in these containers of vector<LogicGate> type.
Moreover each i-th gate has a vector<LogicGate*> next_gate as a member,which is a vector of pointers to i-th gate's next gates, useful for propagate inputs throughout the circuit during simulation.
-Create a Simulator class which gets the instantiated circuit and puts the toplevel inputs in Header-gates, and then makes possible the input signal propagation throughout the internal gates until obtaining the output's Tail-gates, that are the circuit outputs. Finally collects outputs.
Data structures are correctly defined by FileManager only for the first round of inputs. At the second simulation it seems that the conteiner vector<LogicGate*> it's not correctly cleaned even thought I've esplicity done it. Moreover I've cleaned all input's and output's datas of circuit.
Here are the significant code:
Thank you
an exemple:
description.txt
NAME Full_adder
INPUTS 3
OUTPUTS 2
NETS 4
GATES
XOR2 U0 I0, I1, N0
XOR2 U1 N0, I2, O0
AND2 U2 N0, I2, N1
AND2 U3 I0, I1, N2
OR2 U4 N1, N2, O1
input.txt
011
000
110
111
Here what in brief I've done:
-Create a class FileManager that manages the two input files and creates 3 data structures: one concerning inputs, one the top level description, and the other one concerning the internal structural view of circuit
-Create a class Synthesizer that gets the 3 data-structures and synthesize the circuit as a sort of graph, in which the wiring with next gates are done by means of pointer to next gates.
In particulare for each line after "GATES" the synthesizer instatiates a logic gate described by a LogicGate class, and evaluetes which type of port is it: HEADER(inputs labeled as "Ix"), INTERNAL ("Nx") or TAIL. Then collects these logic gates in these containers of vector<LogicGate> type.
Moreover each i-th gate has a vector<LogicGate*> next_gate as a member,which is a vector of pointers to i-th gate's next gates, useful for propagate inputs throughout the circuit during simulation.
-Create a Simulator class which gets the instantiated circuit and puts the toplevel inputs in Header-gates, and then makes possible the input signal propagation throughout the internal gates until obtaining the output's Tail-gates, that are the circuit outputs. Finally collects outputs.
Data structures are correctly defined by FileManager only for the first round of inputs. At the second simulation it seems that the conteiner vector<LogicGate*> it's not correctly cleaned even thought I've esplicity done it. Moreover I've cleaned all input's and output's datas of circuit.
Here are the significant code:
Thank you
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