Quick question. Related to verilog not C++

[merm]

I just thought I would post this question here since it is similar notation to C++.

We can use a multiplexer too in the code.

1. You must name the ALU module and the connections must be in this order: 4bitALU(C, O, A, B,Switch)
(a) C is 1 bit output that is used for the carry bit
(b) O is 4 bit output that is used for the output
(c) A is 4 bit input that is the first term (i.e. A + B = CO)
(d) B is 4 bit input that is the second term (i.e. A + B = CO)
(e) Switch is 4 bit input that controls which operation will be output
2. Switch = 0000 performs bitwise NOT operation on A and outputs it, carry bit is don’t care state
3. Switch = 0001 performs bitwise AND operation on A and B and outputs it, carry bit is don’t care
state
4. Switch = 0010 performs bitwise OR operation on A and B and outputs it, carry bit is don’t care state
5. Switch = 0011 performs bitwise XOR operation on A and B and outputs it, carry bit is don’t care
state
6. Switch = 1000 performs binary addition on A and B and outputs it along with proper carry bit