Maybe I am reading this wrong, but it seems like there is confusion about what a makefile is. I say this because you are blaming compile errors upon make errors.
Edit: It also seems like you solved your problem...
A makefile compiles your code based on rules, which look like this:
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target : prerequisites
recipe
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Make knows how to use g++ to construct a .o from a .cpp. The following example works:
function.h
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#ifndef FUNCTION_H
#define FUNCTION_H
void function( void );
#endif
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function.cpp
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#include "function.h"
#include <iostream>
void function( void )
{
std::cout << "hello\n";
}
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main.cpp
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#include "function.h"
int main( void )
{
function();
return 0;
}
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makefile
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program: main.o function.o
$(CXX) -o $@ $^
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In short, program requires main.o and function.o, which make can use implicit rules to create.
The problem with this is that changes you make to function.h will not require you to rebuild. You can fix this by telling make that main.o and function.o require function.h
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program: main.o function.o
$(CXX) -o $@ $^
main.o: function.h
function.o: function.h
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now you can do:
$ make && touch function.h && make
and the program will build twice.
In no way does adding the prerequisite of function.h to the objects in the makefile mean that you do no need to include function.h in main.cpp or function.cpp.
In short, with that last makefile you wrote, all you need is this:
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all: a.exe
a.exe: main.o KE.o usb_api.o
g++ -o $@ $^
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Any problems you have with this are because your code isn't written right.
Edit:
As a side, the implicit rule that make creates is something like this ( from a cpp file):
$(CXX) $(CXXFLAGS) -c -o thing.o thing.cpp
As such, your makefile could look like this if you wanted to get better warnings:
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CXXFLAGS= -Wall
all: a.exe
a.exe: main.o KE.o usb_api.o
$(CXX) -o $@ $^
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And the implicit rules will pick up -Wall as a compile flag