This will compile myprog.cpp as if it had a #define FOOEY 42 as the first line in the file.
You can use variables in a makefile. Unfortunately, makefiles are not very cross-platform capable because they rely upon the active command shell to process the make instructions (the tab-indented lines following a rule).
HOWEVER, compilers typically auto-define macros to identify the OS to you. For example, if you are compiling on Linux, you can know it without any effort on your part other than simply checking:
Hi,
I have a complex project (100 source files) and I have a make file from the format
SRCS= a.cpp b.cpp .....
%.o : %.c
gcc -c -MD -o $@ $<
@cp $*.d $*.P; \
sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
-e '/^$$/ d' -e 's/$$/ :/' < $*.d >> $*.P; \
rm -f $*.d
However, I receceive a compilation error :
In a.cpp: error no matching function for call to b::foo(int&)
candidates are: b::foo(int)
No, you are most likely trying to pass a constant value to a function taking a (non-const) reference. See if you have a line "b::foo(5)" or something like that anywhere.
BTW, it is not very polite tho hijack someones post like this. If you still have problems please create a new topic.
10X for your reply. (i didnt find how to create a new topic).
However, my problem is exactly the opposite. I'm trying to pass a value to a function who's signature is : void b::foo(int i);
and the function call: int j=8;
b::foo(j);
According to the compiler the function call is ::
b::foo(int&)
and the candidate : b::foo(int)
The code do compile in visual studio, but not in linux!